1. Field of the Invention
The present invention relates to semiconductor wafer testing, and more particularly to a recursive method for classification of wafers.
2. Description of Prior Art
Reliability and quality are at the core of the semiconductor chip industry. To ensure that these characteristics exist in the large number of chips produced, a method is needed to classify chips quickly and accurately. Classification is used to recognize failures and to implement the appropriate corrective procedures to prevent the reoccurrence of those failures.
Typically, the evaluation of wafer test results needs a significant amount of engineering work, especially in high-volume production sites. Manual tasks performed by trained engineers include, for example, estimation, trending and pareto diagnostics. Automated classification of failure patterns on the wafers can release those resources (engineers). Further, the results of manual diagnostics are subject to bias associated with an individual engineer's judgment. An automated method could eliminate such bias.
Ongoing development of neural networks, as a method to characterize failure mechanisms, is computationally expensive and is not available to semiconductor chip manufacturers at this time.
Therefore, a need exists for a method and apparatus for detecting failure patterns on semiconductor wafers, while providing accurate figures related to the detection of failure patterns, for example, related yield loss, and also generating yield loss pareto charts with improved accuracy.